The present invention relates generally to spacecraft simulation, and more particularly to systems for non-intrusive memory transfers for embedded processor-based systems.
The increasing size and complexity of various spacecraft and control subsystems therefore have created a need for detailed validation and verification before deployment. Examples of spacecraft subsystems requiring validation and verification include: (i) multiprocessor-based systems which can have complex software architectures; (ii) fault detection and response systems providing extended autonomous operations; (iii) multiple-articulated payloads and multibody control; (iv) precision payload pointing systems with multiple interacting elements; and (v) sophisticated ground software for automated spacecraft operations.
However, system-level ground testing to verify full system performance of a spacecraft can be costly and/or inadequate. Present implementations of hardware-in-the-loop systems to provide ground testing require special purpose interface hardware and harnessing to create a test environment whereby system hardware or emulations thereof can be integrated with high-fidelity, non-linear, real-time simulations and then instrumented to facilitate verification and validation testing.
Embedded processors and software that constitute various spacecraft subsystems implement asynchronous, real-time processes that require non-intrusive instrumentation to facilitate adequate testing. It is imperative that the real-time behavior of the systems under test not be compromised by instrumentation. Otherwise, the system under test is not truly the system to be used operationally.
Known implementations of such systems required a substantial amount of harnessing and interfacing devices to accommodate non-intrusive instrumentation; typically embedded processor memory monitoring and control. The amount of harnessing and interfacing devices reduces the overall reliability of the system and increases the cost. Known systems employ bus monitoring schemes to facilitate memory monitoring. More capable mechanisms may allow for memory modification. However, these do not operate on a real time basis. That is, the previous implementations have resident arbitration schemes that control access to the data buses. These arbitration schemes initiate wait states that are not found in actual running. Thus, known systems employ complex mechanisms to monitor the contents of embedded processor memories and implement intrusive mechanisms to modify memory.
U.S. Pat. No. 5,808,921 is commonly assigned and was co-invented by the inventor of the present invention. In the ""921 patent, a system for selected and limited, non-intrusive (input/output) I/O access was provided when the CPU was in a memory cycle. The dual port memory mimicked the I/O buffer. Thus, when the ""921 system was in a memory cycle, it was not using the I/O and thus data was transferred via the I/O. Thus, the dual port memory emulated the I/O space. The U.S. Pat. No. 5,808,921 has limited functionality because only the I/O space is emulated and only a portion thereof. U.S. Pat. No. 5,808,921 is hereby incorporated by reference.
It would therefore be desirable to increase the functionality of a simulator and to provide a method and apparatus for providing non-intrusive memory access without extraneous wait states so that crucial instrumentation, in the form of memory status and control, on the embedded, real-time application, can be performed in support of overall system verification and validation.
It is an object of the present invention to provide a low-cost, reliable system for verifying an embedded processor-based system which emulates the entire memory and which requires less facility resources (e.g. test equipment) in comparison to previously-implemented hardware-in-the-loop systems.
A further object of the present invention is to provide a system for testing an embedded processor-based system which does not require special purpose interface hardware and harnessing to integrate the embedded processor-based system with instrumentation to monitor the contents of embedded memories.
In carrying out the above objects, the present invention provides a system for testing an embedded processor, such as an embedded processor for a spacecraft. The system comprises an Emulated Spacecraft Control Processor (ESCP) which contains the embedded processor, a simulation engine, and a host computer. The emulated spacecraft control processor includes a dual-port memory for emulating the input/output interface for the embedded processor and data transfer logic which monitors cycles of the embedded processor to arbitrate access to the dual-port memory, the data transfer logic is operative to allow an access to the dual-port memory when the embedded processor performs a I/O cycle, wherein the access is performed before a subsequent memory cycle of the embedded processor.
In a preferred embodiment, the simulation engine executes program steps asynchronously with respect to the embedded processor. Here, the Emulated Spacecraft Control Processor includes an overlayed dual-port memory for emulating the memory for the embedded processor and data transfer logic which monitors cycles of the embedded processor to arbitrate access to the dual-port memory. The data transfer logic is operative to allow simulation engine access to the dual-port memory when the embedded processor performs an I/O cycle, wherein the access is performed before a subsequent machine cycle of the embedded processor. The data transfer logic is operative to inhibit access by the simulation engine to the dual-port memory when a memory cycle is performed by the embedded processor.
Also in a preferred embodiment, the simulated sensor data, the command data, the actuator command data, and the telemetry data are communicated via an industry standard bus. Here, the system further comprises an interactive bus manager which communicates the command data and the telemetry data between the bus and the host computer. Additionally, the simulated sensor data and actuator command data are communicated between the simulation engine and the Emulated Spacecraft Control Processor using the industry standard bus.
Further in carrying out the above objects, the present invention provides a method of testing an embedded processor based upon the above-described steps.
Embodiments of the present invention are advantageous in that the simulation engine and the Emulated Spacecraft Control Processor share memory space without any compromise of the real-time performance of the embedded processor.
These and other features, aspects, and embodiments of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings.